US 12,131,706 B2
Display device and electronic device including the same
Atsushi Umezaki, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Apr. 2, 2024, as Appl. No. 18/624,254.
Application 18/624,254 is a continuation of application No. 18/371,540, filed on Sep. 22, 2023.
Application 18/371,540 is a continuation of application No. 18/074,584, filed on Dec. 5, 2022, granted, now 11,776,483, issued on Oct. 3, 2023.
Application 18/074,584 is a continuation of application No. 17/665,682, filed on Feb. 7, 2022, granted, now 11,527,208, issued on Dec. 13, 2022.
Application 17/665,682 is a continuation of application No. 17/211,050, filed on Mar. 24, 2021, granted, now 11,250,785, issued on Feb. 15, 2022.
Application 17/211,050 is a continuation of application No. 16/832,606, filed on Mar. 27, 2020, granted, now 10,971,075, issued on Apr. 6, 2021.
Application 16/832,606 is a continuation of application No. 16/420,430, filed on May 23, 2019, granted, now 10,629,134, issued on Apr. 21, 2020.
Application 16/420,430 is a continuation of application No. 16/010,729, filed on Jun. 18, 2018, granted, now 10,304,873, issued on May 28, 2019.
Application 16/010,729 is a continuation of application No. 15/874,245, filed on Jan. 18, 2018, granted, now 10,008,519, issued on Jun. 26, 2018.
Application 15/874,245 is a continuation of application No. 15/145,908, filed on May 4, 2016, granted, now 9,941,308, issued on Apr. 10, 2018.
Application 15/145,908 is a continuation of application No. 14/552,547, filed on Nov. 25, 2014, granted, now 9,337,184, issued on May 10, 2016.
Application 14/552,547 is a continuation of application No. 13/769,999, filed on Feb. 19, 2013, granted, now 8,902,374, issued on Dec. 2, 2014.
Application 13/769,999 is a continuation of application No. 12/614,852, filed on Nov. 9, 2009, granted, now 8,902,144, issued on Dec. 2, 2014.
Claims priority of application No. 2008-304124 (JP), filed on Nov. 28, 2008.
Prior Publication US 2024/0265879 A1, Aug. 8, 2024
Int. Cl. G09G 3/3266 (2016.01); G02F 1/1362 (2006.01); G09G 3/34 (2006.01)
CPC G09G 3/3266 (2013.01) [G02F 1/13624 (2013.01); G02F 1/136286 (2013.01); G09G 3/3413 (2013.01); G09G 2310/0286 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first transistor;
a second transistor;
a third transistor;
a fourth transistor;
a fifth transistor; and
a sixth transistor,
wherein one of a source and a drain of the first transistor is electrically connected to a gate line,
wherein the other of the source and the drain of the first transistor is electrically connected to a clock signal line,
wherein one of a source and a drain of the second transistor is supplied with a power supply voltage,
wherein the other of the source and the drain of the second transistor is electrically connected to the gate line,
wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor,
wherein the other of the source and the drain of the third transistor is electrically connected to a wiring,
wherein one of a source and a drain of the fourth transistor is electrically connected to a power supply line,
wherein the other of the source and the drain of the fourth transistor is electrically connected to the gate of the first transistor,
wherein one of a source and a drain of the fifth transistor is electrically connected to the power supply line,
wherein the other of the source and the drain of the fifth transistor is electrically connected to the gate of the first transistor,
wherein a gate of the fifth transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the sixth transistor is electrically connected to the power supply line,
wherein the other of the source and the drain of the sixth transistor is electrically connected to a gate of the fourth transistor,
wherein a gate of the sixth transistor is electrically connected to the gate of the first transistor,
wherein in a top view, an area where a first conductive layer serving as the one of the source and the drain of the first transistor and a second conductive layer serving as the gate of the first transistor overlap with each other is larger than an area where a third conductive layer serving as the other of the source and the drain of the first transistor and the second conductive layer overlap with each other,
wherein in a top view, the first conductive layer comprises a first region sandwiched between the third conductive layer in the area where the first conductive layer and the second conductive layer overlap with each other,
wherein in a top view, the third conductive layer comprises a second region sandwiched between the first conductive layer in the area where the third conductive layer and the second conductive layer overlap with each other, and
wherein a width of the first conductive layer in the first region is larger than a width of the third conductive layer in the second region.