US 12,131,705 B2
Gate driver and electroluminescent display apparatus including the same
Sung Wook Chang, Paju-si (KR)
Assigned to LG Display Co., Ltd., Seoul (KR)
Filed by LG Display Co., Ltd., Seoul (KR)
Filed on May 22, 2023, as Appl. No. 18/200,463.
Application 18/200,463 is a continuation of application No. 17/742,011, filed on May 11, 2022, granted, now 11,694,629.
Claims priority of provisional application 63/187,927, filed on May 12, 2021.
Prior Publication US 2023/0298530 A1, Sep. 21, 2023
Int. Cl. G09G 3/3233 (2016.01); G09G 3/3266 (2016.01)
CPC G09G 3/3266 (2013.01) [G09G 2300/043 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An electroluminescent display apparatus comprising:
a pixel including a driving transistor, an organic light emitting diode connected to the driving transistor, and at least one switching transistor having a semiconductor layer different from a semiconductor layer of the driving transistor and connected to the driving transistor; and
a gate stage connected to the pixel through a gate line and supplying a scan signal to a gate electrode of the switching transistor;
wherein the gate stage includes a scan generating circuit configured to generate the scan signal and a carry generating circuit configured to generate a carry signal by sharing a first clock signal and a second clock signal having different phases with the scan generating circuit, and
wherein the carry generating circuit includes:
a carry output node through which the carry signal is output;
a first carry transistor connected between an input terminal of the first clock signal and the carry output node and turned on or off according to a voltage of a first carry control node;
a second carry transistor connected between the carry output node and an input terminal of a gate high voltage and turned on or off according to a voltage of a second carry control node;
a node controller configured to control a voltage of the first carry control node and a voltage of the second carry control node based on the first clock signal and the second clock signal;
a first carry capacitor connected to the first carry control node and the carry output node; and
a second carry capacitor connected to the second carry control node and the input terminal of the gate high voltage.