US 12,131,683 B2
Method and device for clock calibration, and storage medium
Xin Duan, Beijing (CN); Jigang Sun, Beijing (CN); Shaolei Zong, Beijing (CN); and Wei Sun, Beijing (CN)
Assigned to Beijing BOE Display Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed by Beijing BOE Display Technology Co., Ltd., Beijing (CN); and BOE Technology Group Co., Ltd., Beijing (CN)
Filed on Oct. 9, 2021, as Appl. No. 17/497,920.
Claims priority of application No. 202011074390.9 (CN), filed on Oct. 9, 2020.
Prior Publication US 2022/0114944 A1, Apr. 14, 2022
Int. Cl. G09G 3/20 (2006.01); G06F 1/08 (2006.01); G06F 1/12 (2006.01); G06F 1/14 (2006.01)
CPC G09G 3/2092 (2013.01) [G06F 1/08 (2013.01); G06F 1/12 (2013.01); G06F 1/14 (2013.01); G09G 2310/08 (2013.01); G09G 2340/0435 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method for clock calibration, applicable to a controller, the method comprising:
sending display data to a target driving chip based on an initial clock frequency, the target driving chip comprising a plurality of clock calibration circuits, each of the clock calibration circuits being configured with one clock frequency;
sending a configuration instruction to the target driving chip, the configuration instruction comprising a reference clock frequency; and
sending a clock calibration signal of a first target clock frequency to the target driving chip, the first target clock frequency being different from the initial clock frequency, wherein
the configuration instruction is configured to instruct the target driving chip to adjust a local clock frequency of the target driving chip to the first target clock frequency by a target clock calibration circuit, and a difference between a clock frequency configured for the target clock calibration circuit and the reference clock frequency is less than a difference between a clock frequency configured for other clock calibration circuits in the target driving chip and the reference clock frequency.