US 12,131,154 B2
Systems and methods for performing instructions to convert to 16-bit floating-point format
Alexander F. Heinecke, San Jose, CA (US); Robert Valentine, Kiryat Tivon (IL); Mark J. Charney, Lexington, MA (US); Raanan Sade, Kibutz Sarid (IL); Menachem Adelman, Haifa (IL); Zeev Sperber, Zichron Yackov (IL); Amit Gradstein, Binyamina (IL); and Simon Rubanovich, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 28, 2022, as Appl. No. 17/851,468.
Application 17/851,468 is a continuation of application No. 16/186,384, filed on Nov. 9, 2018, granted, now 11,372,643, issued on Jun. 28, 2022.
Prior Publication US 2022/0326948 A1, Oct. 13, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01)
CPC G06F 9/30025 (2013.01) [G06F 9/30014 (2013.01); G06F 9/30018 (2013.01); G06F 9/30036 (2013.01); G06F 9/30038 (2023.08); G06F 9/30105 (2013.01); G06F 9/3802 (2013.01); G06F 9/3818 (2013.01); G06F 9/384 (2013.01); G06F 9/3887 (2013.01); G06F 9/3888 (2023.08)] 24 Claims
OG exemplary drawing
 
1. A processor comprising:
fetch circuitry to fetch a vector conversion instruction having fields to specify an opcode and locations of a first source vector comprising a first plurality of single-precision elements that are each a 32-bit floating point format of a sign bit, an 8-bit exponent, and a 24-bit significand, a second source vector comprising a second plurality of single-precision elements that are each the 32-bit floating point format of the sign bit, the 8-bit exponent, and the 24-bit significand, and a single destination vector comprising a number of 16-bit floating-point elements that is at least a number of the first plurality and the second plurality, the opcode to indicate execution circuitry is to convert each of the 32-bit floating point format elements of the first source vector and the second source vector to a half-precision 16-bit floating-point format of a sign bit, a 5-bit exponent, and an 11-bit significand, and to store each converted element into a corresponding location of the single destination vector as a resultant of the vector conversion instruction;
decode circuitry to decode the fetched instruction; and
the execution circuitry to respond to the decoded instruction as specified by the opcode.