US 12,131,061 B2
Memory system having system buffer and method of storing data by using the system buffer
In Jong Jang, Icheon-si (KR)
Assigned to SK HYNIX INC., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Oct. 21, 2021, as Appl. No. 17/506,931.
Claims priority of application No. 10-2021-0049978 (KR), filed on Apr. 16, 2021.
Prior Publication US 2022/0334761 A1, Oct. 20, 2022
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0656 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system comprising:
a system buffer including buffer areas to which addresses are allocated, and configured to store data in the buffer areas; and
a controller configured to:
extract a first parity bit for data to be stored in the system buffer and a second parity bit from the data stored in the buffer areas;
generate a flag bit according to a comparison between the first parity bit and the second parity bit;
increase a count of an address corresponding to a first flag bit indicating that a defect occurs in a buffer area in which the data is stored, in response to generating the first flag bit as the flag bit;
determine, among the addresses, the address as a defect address when the count of the address is equal to or greater than a reference number; and
block access to the buffer area corresponding to the defect address,
wherein the controller comprises:
a counter configured to store the count associated with the address corresponding to the first flag bit, and output the defect address; and
a defect address storage coupled to the counter and configured to store the defect address output from the counter.