US 12,131,059 B2
Data writing circuit, data writing method, and memory
Xianjun Wu, Hefei (CN); and Weibing Shang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jul. 1, 2022, as Appl. No. 17/855,848.
Application 17/855,848 is a continuation of application No. PCT/CN2022/088684, filed on Apr. 24, 2022.
Claims priority of application No. 202210203725.5 (CN), filed on Mar. 3, 2022.
Prior Publication US 2023/0280931 A1, Sep. 7, 2023
Int. Cl. G06F 3/06 (2006.01); G11C 5/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A data writing circuit, applicable to a memory, the memory comprising a read-write control circuit, a column decoding circuit, and a plurality of storage areas, and the data writing circuit comprising:
a delay generation circuit, configured to generate a sub-grab signal of each storage area based on an initial grab signal and data transmission delay of the storage area, and generate a grab enable signal based on all of the sub-grab signals, wherein
data transmission delay corresponding to the storage area close to the column decoding circuit is less than data transmission delay corresponding to the storage area away from the column decoding circuit;
a time interval between a time of receiving data transmitted by a global data line and a time of receiving a column selection signal for each storage area meets a preset range;
the read-write control circuit is configured to write data on a data bus into the global data line based on the grab enable signal; and
the global data line is configured to transmit the data to the storage area through the column decoding circuit based on the column selection signal.