US 12,131,058 B2
Configurable arithmetic HW accelerator
Yuri Ryabinin, Beer Sheva (IL); and Shay Benisty, Beer Sheva (IL)
Assigned to Sandisk Technologies, Inc., Milpitas, CA (US)
Filed by Western Digital Technologies, Inc., San Jose, CA (US)
Filed on Apr. 22, 2022, as Appl. No. 17/726,755.
Prior Publication US 2023/0342070 A1, Oct. 26, 2023
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0655 (2013.01) [G06F 3/0604 (2013.01); G06F 3/0679 (2013.01)] 12 Claims
OG exemplary drawing
 
1. A data storage device, comprising:
a memory device; and
a controller coupled to the memory device, wherein the controller comprises:
a decoder module;
a plurality of response channels coupled to the decoder module;
an arithmetic pipeline module coupled to the plurality of response channels;
an arbiter module coupled to the plurality of response channels and the arithmetic pipeline module;
a mux module coupled to the arithmetic pipeline module;
a random access memory (RAM) access module coupled to the decoder module and the mux module; and
a RAM coupled to the mux module.