US 12,131,032 B1
Dispatcher for improved-performance non-volatile memory store operations
Li Rosenbaum, Rishon Lezion (IL); Elad Harush, Raanana (IL); and Omri Flint, Ramat Hasharon (IL)
Assigned to APPLE INC., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Nov. 16, 2022, as Appl. No. 17/987,899.
Claims priority of provisional application 63/407,676, filed on Sep. 18, 2022.
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/0616 (2013.01) [G06F 3/0611 (2013.01); G06F 3/0659 (2013.01); G06F 3/0679 (2013.01); G06F 3/0689 (2013.01); G06F 2212/7207 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A System on Chip (SoC), comprising:
a processor, configured to produce store instructions for storing data blocks in a Non-Volatile-Memory (NVM);
a parity generation circuit, configured to calculate parity blocks over the data blocks in accordance with a redundant storage scheme, to send the parity blocks to the NVM, and to produce completion notifications with respect to the parity blocks; and
a dispatcher circuit, configured to dispatch the store instructions to the NVM,
wherein the processor is further configured to send a parity-barrier instruction specifying a synchronization barrier over a data block and a parity block of a given store instruction, and wherein, in accordance with the parity-barrier instruction, the dispatcher circuit is configured to send the data block of the given store instruction to the NVM only after receiving a completion notification corresponding to the parity block of the given store instruction.