US 12,131,026 B2
Adaptive scheduling of memory and processing-in-memory requests
Alexandru Dutu, Kirkland, WA (US); Nuwan S Jayasena, Cupertino, CA (US); and Niti Madan, Bee Cave, TX (US)
Assigned to Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed by Advanced Micro Devices, Inc., Santa Clara, CA (US)
Filed on Dec. 29, 2022, as Appl. No. 18/090,916.
Prior Publication US 2024/0220107 A1, Jul. 4, 2024
Int. Cl. G06F 3/06 (2006.01)
CPC G06F 3/061 (2013.01) [G06F 3/0659 (2013.01); G06F 3/0673 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory module including a memory and a processing-in-memory component;
a host including at least one core; and
a memory controller configured to:
receive a plurality of processing-in-memory requests and a plurality of non-processing-in-memory requests from the host;
schedule an order of execution for the plurality of processing-in-memory requests and the plurality of non-processing-in-memory requests based at least in part on a processing-in-memory request stall threshold and a non-processing-in-memory request stall threshold; and
modifying the processing-in-memory request stall threshold and the non-processing-in-memory request stall threshold in response to the system switching between executing processing-in-memory requests and executing non-processing-in-memory requests.