US 12,131,020 B2
Memory devices and systems including static and dynamic caches, and related methods
Kishore K. Muchherla, Fremont, CA (US); Ashutosh Malshe, Fremont, CA (US); Sampath K. Ratnam, Boise, ID (US); Peter Feeley, Boise, ID (US); Michael G. Miller, Boise, ID (US); Christopher S. Hale, Boise, ID (US); and Renato C. Padilla, Folsom, VA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 3, 2021, as Appl. No. 17/457,615.
Application 17/457,615 is a continuation of application No. 16/396,432, filed on Apr. 26, 2019, granted, now 11,204,696.
Application 16/396,432 is a continuation of application No. 15/269,518, filed on Sep. 19, 2016, granted, now 10,359,933, issued on Jul. 23, 2019.
Prior Publication US 2022/0091740 A1, Mar. 24, 2022
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 3/06 (2006.01); G06F 11/34 (2006.01); G06F 12/02 (2006.01); G06F 12/0888 (2016.01); G06F 12/0893 (2016.01)
CPC G06F 3/0604 (2013.01) [G06F 3/064 (2013.01); G06F 3/0653 (2013.01); G06F 3/0679 (2013.01); G06F 11/34 (2013.01); G06F 11/348 (2013.01); G06F 12/0246 (2013.01); G06F 12/0888 (2013.01); G06F 12/0893 (2013.01); G06F 2201/885 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/1044 (2013.01); G06F 2212/222 (2013.01); G06F 2212/502 (2013.01); G06F 2212/601 (2013.01); G06F 2212/7205 (2013.01); G06F 2212/7206 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory array including dynamic cache and static cache; and a memory controller configured to:
completely disable the static cache of the memory array responsive to a number of program/erase (PE) cycles consumed by the static cache being greater than an endurance of the static cache such that writes are only directed to the dynamic cache; and
completely disable the dynamic cache of the memory array responsive to a number of PE cycles consumed by the dynamic cache being greater than an endurance of the dynamic cache such that writes are only directed to the static cache;
wherein the static cache includes single-level cell (SLC) blocks of the memory array of the memory device, and the dynamic cache and a main memory of the memory device share at least a portion of x-level cell (XLC) blocks of the memory array, wherein x represents an integer greater than one.