US 12,130,915 B2
Microarchitectural mechanisms for the prevention of side-channel attacks using a thread identification (TID) and a privilege level bit
Robert S. Chappell, Portland, OR (US); Jared W. Stark, IV, Portland, OR (US); Joseph Nuzman, Haifa (IL); Stephen Robinson, Austin, TX (US); and Jason W. Brandt, Austin, TX (US)
Assigned to Intel CORPORATION, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 1, 2022, as Appl. No. 17/590,470.
Application 17/590,470 is a continuation of application No. 16/456,578, filed on Jun. 28, 2019, granted, now 11,238,155, issued on Feb. 1, 2022.
Claims priority of provisional application 62/691,511, filed on Jun. 28, 2018.
Prior Publication US 2022/0335126 A1, Oct. 20, 2022
Int. Cl. G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 9/48 (2006.01); G06F 12/0802 (2016.01); G06F 21/55 (2013.01); G06F 21/62 (2013.01)
CPC G06F 21/556 (2013.01) [G06F 9/30116 (2013.01); G06F 9/30123 (2013.01); G06F 9/30196 (2013.01); G06F 9/3806 (2013.01); G06F 9/3808 (2013.01); G06F 9/3842 (2013.01); G06F 9/3844 (2013.01); G06F 9/4881 (2013.01); G06F 12/0802 (2013.01); G06F 21/62 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A processor core comprising:
an instruction fetch circuit to fetch instructions;
storage for a data structure comprising a plurality of entries that each include a thread identification (TID) and a privilege level bit; and
a branch predictor, coupled to the instruction fetch circuit and the storage, to predict a target instruction corresponding to a branch instruction based on at least one entry of the plurality of entries in the storage, and cause the target instruction to be fetched by the instruction fetch circuit.