US 12,130,758 B2
Data transmission power optimization
Tomer Shoshani, Tel-Aviv (IL); Albert Yosher, Tel Mond (IL); and Yaron Shachar, Raanana (IL)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Aug. 24, 2022, as Appl. No. 17/821,935.
Prior Publication US 2024/0070095 A1, Feb. 29, 2024
Int. Cl. G06F 13/16 (2006.01); G06F 13/38 (2006.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/1689 (2013.01) [G06F 13/4068 (2013.01)] 12 Claims
OG exemplary drawing
 
1. An integrated circuit (IC) comprising:
an input configured to receive a radio frequency (RF) signal from an antenna;
an output bus interface configured to be coupled to a plurality of lanes in a communication bus configured to carry signals from the IC to a remote processor;
a memory structure comprising an input/output (I/O) pin and a plurality of memory banks, the memory structure configured to:
receive a first packet from a channel through the I/O pin,
partition the first packet into a plurality of units equal in number to the plurality of memory banks; and
store the plurality of units into corresponding ones of the plurality of memory banks;
an input multiplexer communicatively positioned between the input and the I/O pin; and
an output multiplexer communicatively positioned between the memory structure and the output bus interface while being separate and distinct therefrom, the output multiplexer configured to reassemble the first packet from the plurality of memory banks and route the first packet to a lane in the communication bus through the output bus interface.