US 12,130,748 B2
Caching of logical-to-physical mapping information in a memory sub-system
Sanjay Subbarao, Irvine, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jul. 25, 2023, as Appl. No. 18/225,958.
Application 18/225,958 is a continuation of application No. 17/203,017, filed on Mar. 16, 2021, granted, now 11,734,189.
Prior Publication US 2023/0367719 A1, Nov. 16, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 12/10 (2016.01); G06F 12/0875 (2016.01); G06F 12/1009 (2016.01)
CPC G06F 12/1009 (2013.01) [G06F 12/0875 (2013.01); G06F 2212/608 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device; and
a processing device coupled to the memory device, the processing device comprising a primary flash translation layer (FTL) and a secondary FTL, the primary FTL configured to perform operations comprising:
receiving a request specifying a logical address associated with a host-initiated operation directed at a first portion of the memory device; and
providing a look-up request to the secondary FTL based on the request, the look-up request specifying the logical address;
the secondary FTL configured to perform operations comprising:
accessing, from a volatile memory component, a logical to physical (L2P) table comprising a mapping between logical addresses and physical addresses in a second portion of the memory device;
determining an entry in the L2P table that corresponds to the logical address points to an entry in a read cache table;
identifying, based on a chunk in a read cache corresponding to a chunk address determined based an entry number of the entry in the read cache table, a physical address that corresponds to the logical address specified by the request, the physical address corresponding to a physical location in the first portion of memory device; and
providing the physical address to the primary FTL responsive to the look-up request, the primary FTL further configured to execute the host-initiated operation at the physical location within the first portion of the memory device corresponding the physical address that corresponds to the logical address specified by the request.