| CPC G06F 12/0873 (2013.01) [G06F 12/0253 (2013.01)] | 14 Claims |
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1. A method for performing data access management of a memory device in a predetermined communications architecture with aid of unbalanced table search, the method being applied to a memory controller of the memory device, the memory device comprising the memory controller and a non-volatile (NV) memory, the NV memory comprising at least one NV memory element, the at least one NV memory element comprising a plurality of blocks, the method comprising:
utilizing the memory controller to receive a plurality of host commands from a host device through a transmission interface circuit of the memory controller, perform the unbalanced table search to receive a set of first data and a set of second data with a first active block and a second active block among the plurality of blocks according to a set of first commands and a set of second commands among the plurality of host commands, respectively, and update a first temporary physical-to-logical (P2L) address mapping table corresponding to the first active block and a second temporary P2L address mapping table corresponding to the second active block, wherein the set of first commands and the set of second commands indicate that writing the set of first data into the memory device and writing the set of second data into the memory device are requested, respectively, and the unbalanced table search comprises searching for any logical address of any first data among the set of first data received with the first active block in the second temporary P2L address mapping table corresponding to the second active block, without searching for any logical address of any second data among the set of second data received with the second active block in the first temporary P2L address mapping table corresponding to the first active block; and
selectively updating a first P2L address mapping table and a second P2L address mapping table in the NV memory according to the first temporary P2L address mapping table and the second temporary P2L address mapping table, respectively, for performing subsequent processing, wherein the first temporary P2L address mapping table and the second temporary P2L address mapping table are arranged to occupy a first table region of a first size and a second table region of a second size in a Random Access Memory (RAM) within the memory controller, respectively.
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