US 12,130,740 B2
Apparatuses and methods for a processor architecture
Jason W. Brandt, Austin, TX (US); Robert S. Chappell, Portland, OR (US); Jesus Corbal, King City, OR (US); Edward T. Grochowski, San Jose, CA (US); Stephen H. Gunther, Beaverton, OR (US); Buford M. Guy, Austin, TX (US); Thomas R. Huff, Hillsboro, OR (US); Christopher J. Hughes, Santa Clara, CA (US); Elmoustapha Ould-Ahmed-Vall, Chandler, AZ (US); Ronak Singhal, Portland, OR (US); Seyed Yahya Sotoudeh, San Jose, CA (US); Bret L. Toll, Hillsboro, OR (US); Lihu Rappoport, Haifa (IL); David B. Papworth, Cornelius, OR (US); and James D. Allen, Austin, TX (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 4, 2022, as Appl. No. 17/712,632.
Application 17/712,632 is a continuation of application No. 16/115,067, filed on Aug. 28, 2018, granted, now 11,294,809.
Application 16/115,067 is a continuation of application No. 15/376,647, filed on Dec. 12, 2016, granted, now 10,282,296, issued on May 7, 2019.
Prior Publication US 2022/0237123 A1, Jul. 28, 2022
Int. Cl. G06F 12/0831 (2016.01); G06F 9/30 (2018.01); G06F 9/38 (2018.01); G06F 12/1009 (2016.01); G06F 12/1027 (2016.01)
CPC G06F 12/0831 (2013.01) [G06F 9/30043 (2013.01); G06F 9/384 (2013.01); G06F 12/1009 (2013.01); G06F 12/1027 (2013.01); G06F 2212/1016 (2013.01); G06F 2212/621 (2013.01); G06F 2212/68 (2013.01)] 15 Claims
OG exemplary drawing
 
1. A processor comprising:
an instruction decoder configured to decode a plurality of instructions to be executed by an execution unit;
register renaming circuitry configured to eliminate move instructions from the plurality of instructions to be executed by the execution unit, the register renaming circuitry including a register alias table (RAT) including a plurality of entry locations, at least one of the entry locations including a physical register file identifier field, a sign-extend indicator field, a zero-extend indicator field, and a zero indicator field; and
a multiplexer configured to select between a modified source operand and an unmodified source operand for use by the execution unit, wherein the selection is based on the sign-extend indicator, the zero-extend indicator, and the zero indicator.