US 12,130,738 B2
Compressed cache memory with decompress on fault
Vedvyas Shanbhogue, Austin, TX (US); Jayesh Gaur, Bangalore (IN); Wajdi K. Feghali, Boston, MA (US); Vinodh Gopal, Westborough, MA (US); and Utkarsh Kakaiya, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 22, 2020, as Appl. No. 17/130,632.
Prior Publication US 2022/0197793 A1, Jun. 23, 2022
Int. Cl. G06F 12/0802 (2016.01); H03M 7/30 (2006.01)
CPC G06F 12/0802 (2013.01) [H03M 7/60 (2013.01); G06F 2212/401 (2013.01); G06F 2212/60 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a core;
a hardware decompression accelerator (HDA) coupled to the core;
a compressed cache coupled to the core;
a scratchpad memory; and
circuitry coupled to the core and communicatively coupled to each of the HDA, the scratchpad memory and the compressed cache, the circuitry to execute microcode to provide a first page fault handler, comprising the circuitry to:
store to the scratchpad memory a first address to a decompression work descriptor which is to comprise a second address of a compressed page which is stored in the compressed cache;
detect a page fault; and
in response to the page fault:
send a page fault exception to a second page fault handler of an operating system which is executed with the core;
access the scratchpad memory to perform an identification of the first address; and
based on the identification:
retrieve the second address from the decompression work descriptor; and
send to the HDA an enqueue message which comprises the second address, wherein, based on the enqueue message, the HDA is to enqueue one or more instructions to decompress the compressed page at the second address.