| CPC G06F 11/366 (2013.01) | 19 Claims |
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1. A method comprising:
detecting an occurrence of an error in a processor of a multiprocessor device having a plurality of processors;
in response to the error, triggering an inter-processor interrupt from the processor in which the error occurred to each of the other processors of the multiprocessor device to halt operation of the multiprocessor device;
storing a plurality of processor core dumps in a memory subsystem, the plurality of processor core dumps corresponding to the plurality of processors in the multiprocessor device including one or more processors that does not have the error;
determining that a data ready indication for each of the processors has been set to indicate that the corresponding processor core dump has been stored in the memory subsystem; and
copying the plurality of processor core dumps from the memory subsystem to a non-volatile memory to generate a device core dump in the non-volatile memory.
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