US 12,130,724 B2
Closed chassis debugging through tunneling
Gilad Shayevitz, Olesh (IL); Tsvika Kurts, Haifa (IL); Vladislav Kopzon, Haifa (IL); Reuven Rozic, Binyamina (IL); and Yaniv Hayat, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 25, 2020, as Appl. No. 16/912,545.
Prior Publication US 2020/0327041 A1, Oct. 15, 2020
Int. Cl. G06F 11/36 (2006.01); G06F 11/34 (2006.01); G06F 13/38 (2006.01); G06F 13/42 (2006.01)
CPC G06F 11/3636 (2013.01) [G06F 11/3476 (2013.01); G06F 11/3688 (2013.01); G06F 11/3692 (2013.01); G06F 13/385 (2013.01); G06F 13/4282 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a computing device, the computing device comprising a source of trace data, the trace data comprising information about the computing device to be used to debug errors associated with the computing device;
a high-speed trace interface (HTI) to receive the trace data from the computing device;
a serial interface comprising a port, the serial interface interconnected to the HTI by a physical interface;
the computing device to:
establish a host-to-host tunneling connection to a second computing device across a serial link via the port; and
tunnel the trace data from the HTI through the host-to-host tunneling connection to the second computing device
wherein the computing device comprises a processor, wherein the trace data relates to the processor, wherein the processor is to tunnel the trace data from the HTI through the host-to-host tunneling connection without storing the trace data in DRAM of the processor.