US 12,130,651 B2
Current mirror
Renald Boulestin, Grenoble (FR)
Assigned to STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed by STMicroelectronics (Grenoble 2) SAS, Grenoble (FR)
Filed on Aug. 25, 2022, as Appl. No. 17/822,266.
Claims priority of application No. 2108926 (FR), filed on Aug. 26, 2021.
Prior Publication US 2023/0054214 A1, Feb. 23, 2023
Int. Cl. H03M 1/66 (2006.01); G05F 3/26 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01)
CPC G05F 3/262 (2013.01) [H01L 27/088 (2013.01); H01L 29/42376 (2013.01); H03M 1/66 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A current mirror circuit comprising:
a first metal oxide semiconductor (MOS)-type transistor and a second MOS-type transistor assembled as a current mirror;
wherein the first transistor has a first gate length different from a second gate length of the second transistor;
wherein the first transistor comprises a series of a first number of third series-coupled MOS-type transistors, and a sum of the gate lengths of the third transistors is equal to the first gate length; and
wherein the second transistor comprises a series of a second number of fourth series-coupled MOS-type transistors, and a sum of the gate lengths of the fourth transistors is equal to the second gate length.