US 12,130,330 B2
Integrated circuit including constant-0 flip flops reconfigured to provide observable and controllable test points
Paul Policke, Cedar Park, TX (US); and Shwetha Shivashankar Murthy, Pflugerville, TX (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Jan. 25, 2023, as Appl. No. 18/159,486.
Prior Publication US 2024/0248136 A1, Jul. 25, 2024
Int. Cl. G01R 31/3185 (2006.01); G01R 31/3177 (2006.01)
CPC G01R 31/318541 (2013.01) [G01R 31/318538 (2013.01); G01R 31/3177 (2013.01)] 9 Claims
OG exemplary drawing
 
1. An integrated circuit (IC), comprising:
a data path;
a logic gate including a first input coupled to the data path, and a second input configured to receive a test data register (TDR) signal, wherein the logic gate is configured to output data from the data path in response to an asserted TDR signal being asserted or output a constant logic value in response to a deasserted TDR signal; and
a first flip-flop including:
a data input (D) coupled to and configured to receive the data or the constant logic value from an output of the logic gate;
a data output (Q) that is not connected to any functional circuit or logic; and
a scan output (Sout) port coupled to a scan path.