US 12,130,329 B2
Methods and apparatus to implement a boundary scan for shared analog and digital pins
Prasanth Viswanathan Pillai, Bangalore (IN); Swathi Gangasani, Bangalore (IN); and Vaskar Sarkar, Bangalore (IN)
Assigned to Texas Instruments Incorporated, Dallas, TX (US)
Filed by Texas Instruments Incorporated, Dallas, TX (US)
Filed on Feb. 28, 2023, as Appl. No. 18/115,739.
Prior Publication US 2024/0288496 A1, Aug. 29, 2024
Int. Cl. G01R 31/3177 (2006.01); G01R 31/3167 (2006.01); G01R 31/3185 (2006.01)
CPC G01R 31/3177 (2013.01) [G01R 31/3167 (2013.01); G01R 31/318508 (2013.01); G01R 31/318533 (2013.01); G01R 31/318536 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first boundary cell including an input terminal;
an input buffer including an input terminal, an output terminal, and an enable terminal, the output terminal of the input buffer coupled to the input terminal of the first boundary cell;
a general purpose input output (GPIO) circuit that includes a select terminal;
a logic gate including an input terminal and an output terminal, the input terminal of the logic gate coupled to the select terminal of the GPIO circuit; and
a second boundary cell including an input terminal and an output terminal, the input terminal of the second boundary cell coupled to the output terminal of the logic gate and the output terminal of the second boundary cell coupled to the enable terminal of the input buffer.