US 7,545,037 C1 (12,752nd)
Semiconductor chips having redistributed power/ground lines directly connected to power/ground lines of internal circuits and methods of fabricating the same
Jong-Joo Lee, Gyeonggi-do (KR)
Filed by Jong-Joo Lee, Gyeonggi-do (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Reexamination Request No. 90/015,298, Sep. 11, 2023.
Reexamination Certificate for Patent 7,545,037, issued Jun. 9, 2009, Appl. No. 11/378,899, Mar. 17, 2006.
Claims priority of application No. 10-2005-0022787 (KR), filed on Mar. 18, 2005.
Ex Parte Reexamination Certificate issued on Oct. 24, 2024.
Int. Cl. H10B 12/00 (2023.01); H01L 21/84 (2006.01); H01L 23/528 (2006.01); H01L 27/12 (2006.01)
CPC H10B 12/09 (2023.02) [H01L 21/84 (2013.01); H01L 23/5286 (2013.01); H01L 27/1203 (2013.01); H01L 2224/05548 (2013.01); H01L 2224/05552 (2013.01); H01L 2224/05567 (2013.01); H01L 2224/05571 (2013.01); H01L 2924/00014 (2013.01); H01L 2924/0002 (2013.01)]
OG exemplary drawing
AS A RESULT OF REEXAMINATION, IT HAS BEEN DETERMINED THAT:
The patentability of claim 12 is confirmed.
Claims 1-11 and 13-15 are cancelled.
12. The method according to claim 7, wherein the main metal pattern is formed by sequentially stacking a copper layer, a diffusion barrier layer, and a gold layer, wherein the diffusion barrier layer comprises a metal layer for preventing interaction of the copper layer and the gold layer.