US 12,457,911 B2
Semiconductor-superconductor hybrid devices with a horizontally-confined channel and methods of forming the same
Geoffrey Charles Gardner, West Lafayette, IN (US); Sergei Vyatcheslavovich Gronin, West Lafayette, IN (US); Flavio Griggio, Seattle, WA (US); Raymond Leonard Kallaher, West Lafayette, IN (US); Noah Seth Clay, West Lafayette, IN (US); and Michael James Manfra, West Lafayette, IN (US)
Assigned to Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed by Microsoft Technology Licensing, LLC, Redmond, WA (US)
Filed on Nov. 22, 2021, as Appl. No. 17/532,811.
Prior Publication US 2023/0165167 A1, May 25, 2023
Int. Cl. H10N 60/10 (2023.01); H10N 60/01 (2023.01)
CPC H10N 60/128 (2023.02) [H10N 60/0632 (2023.02)] 19 Claims
OG exemplary drawing
 
1. A semiconductor-superconductor hybrid device comprising:
a semiconductor heterostructure formed over a substrate;
a superconducting layer formed over the semiconductor heterostructure;
a first gate, having a first top surface, formed adjacent to a first side of the semiconductor heterostructure; and
a second gate, having a second top surface, formed adjacent to a second side, opposite to the first side, of the semiconductor heterostructure, wherein each of the first top surface of the first gate and the second top surface of the second gate is offset vertically from a top surface of the semiconductor heterostructure by a predetermined offset amount, wherein the semiconductor-superconductor hybrid device is configured to form a horizontally-confined electrostatic channel in the semiconductor heterostructure in response to an application of an electric field to the semiconductor heterostructure via the first gate and the second gate, wherein the predetermined offset amount is selected to ensure that the horizontally-confined electrostatic channel is formed at a selected distance from the top surface of the semiconductor heterostructure to reduce an effect of any structural disorder associated with an interface of the superconducting layer with the semiconductor heterostructure, and wherein the structural disorder associated with the interface comprises line edge roughness (LER) associated with the superconducting layer.