| CPC H10N 50/10 (2023.02) [H10B 61/00 (2023.02); H10N 50/01 (2023.02); H10N 50/80 (2023.02)] | 12 Claims |

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1. A semiconductor structure for a magnetoresistive random-access memory (MRAM) device, the semiconductor structure comprising:
a bottom electrode under a magnetic tunnel junction (MTJ) pillar, wherein an electrode material of the bottom electrode extends vertically towards an interlayer dielectric layer and the electrode material surrounds a spacer, wherein the spacer encapsulates the MTJ pillar and wherein the bottom electrode have one of a round shape or an oval shape;
a top electrode on the MTJ pillar, wherein the top electrode is thinner than the bottom electrode and wherein the top electrode have one of a round shape or an oval shape; and
a metal contact with a liner is disposed over the top electrode on the MTJ pillar.
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