| CPC H10N 50/01 (2023.02) [H10B 61/00 (2023.02); H10N 50/10 (2023.02); H10N 50/80 (2023.02)] | 5 Claims |

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1. An integrated circuit comprising:
a dielectric layer;
a bottom contact disposed at least partially in the dielectric layer, the bottom contact having an upper surface;
two dielectric sidewall spacers disposed on the bottom contact;
a landing pad disposed on the bottom contact and between the two dielectric sidewall spacers, wherein a maximum width of the landing pad at a top surface of the landing pad is smaller than a width of the bottom contact at an interface between the landing pad and the bottom contact; and
a magnetic tunnel junction disposed directly on top of the landing pad;
wherein the upper surface of the bottom contact is wider than the magnetic tunnel junction; and
wherein:
the landing pad is separately formed on the upper surface of the bottom contact;
the landing pad is formed from a landing pad material selected from the group consisting of niobium, niobium nitride, tungsten, tungsten nitride, titanium, titanium nitride, ruthenium, and molybdenum;
the bottom contact includes a bottom contact liner and a bottom contact core, wherein the bottom contact core is formed from a bottom contact core material selected from the group consisting of copper, cobalt, ruthenium, copper-manganese, and aluminum; and
the upper surface of the bottom contact bottom contact has an equal width as does the landing pad plus the dielectric sidewall spacers.
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