| CPC H10K 59/1315 (2023.02) [H10K 59/131 (2023.02)] | 15 Claims |

|
1. A display panel, comprising a base substrate and a drive array layer located on the base substrate, wherein the drive array layer comprises a thin film transistor and a plurality of voltage drain drain signal lines, the thin film transistor comprises a bottom gate and a top gate opposite to each other and a source electrode and a drain electrode located on two sides of the top gate, the voltage drain drain signal lines are arranged on a same layer as the source electrode and the drain electrode,
the drive array layer further comprises a plurality of voltage dividing wires arranged on a same layer as the bottom gate, the plurality of voltage dividing wires and the plurality of voltage drain drain signal lines intersect with one another to be in grid-shaped distribution, and at least part of intersecting positions of the voltage dividing wires and the voltage drain drain signal lines are electrically connected through via holes.
|