US 12,457,855 B2
Display device and electronic device
Manabu Sato, Oyama (JP); Hironori Matsumoto, Tochigi (JP); and Masataka Nakada, Tochigi (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Sep. 19, 2024, as Appl. No. 18/889,614.
Application 18/889,614 is a continuation of application No. 18/138,765, filed on Apr. 25, 2023, granted, now 12,101,966.
Claims priority of application No. 2022-075019 (JP), filed on Apr. 28, 2022.
Prior Publication US 2025/0017043 A1, Jan. 9, 2025
Int. Cl. G06F 3/041 (2006.01); G06F 3/042 (2006.01); G06V 40/13 (2022.01); G09G 3/3233 (2016.01); H10K 39/34 (2023.01); H10K 59/121 (2023.01)
CPC H10K 59/1213 (2023.02) [G06F 3/0412 (2013.01); G06F 3/042 (2013.01); G06V 40/1318 (2022.01); G09G 3/3233 (2013.01); H10K 39/34 (2023.02); G06F 2203/04108 (2013.01); G09G 2300/0852 (2013.01); G09G 2354/00 (2013.01)] 3 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
an A/D converter circuit, the A/D converter circuit comprising:
a first transistor; and
a second transistor,
wherein the semiconductor device comprises:
a first conductive layer and a second conductive layer over a substrate;
a first insulating layer over and in contact with the first conductive layer and the second conductive layer;
a second insulating layer over the first insulating layer;
a third insulating layer over the second insulating layer;
a third conductive layer and a fourth conductive layer over the third insulating layer;
a first semiconductor layer over and in contact with the third conductive layer;
a second semiconductor layer over and in contact with the fourth conductive layer;
a fourth insulating layer over the first semiconductor layer and the second semiconductor layer; and
a fifth conductive layer and a sixth conductive layer over the fourth insulating layer,
wherein the first conductive layer comprises a region configured to function as one of a source electrode and a drain electrode of the first transistor,
wherein the second conductive layer comprises a region configured to function as one of a source electrode and a drain electrode of the second transistor,
wherein the third conductive layer comprises a region configured to function as the other of the source electrode and the drain electrode of the first transistor,
wherein the fourth conductive layer comprises a region configured to function as the other of the source electrode and the drain electrode of the second transistor,
wherein each of the first conductive layer and the second conductive layer comprises a metal oxide,
wherein the first semiconductor layer is in contact with the first conductive layer in a first opening provided in the first insulating layer, the second insulating layer, and the third insulating layer,
wherein the second semiconductor layer is in contact with the second conductive layer in a second opening provided in the first insulating layer, the second insulating layer, and the third insulating layer,
wherein the fifth conductive layer comprises a region configured to function as a gate electrode of the first transistor,
wherein the sixth conductive layer comprises a region configured to function as a gate electrode of the second transistor,
wherein the sixth conductive layer is electrically connected to the first conductive layer via the fourth conductive layer, and
wherein the fifth conductive layer is electrically connected to the third conductive layer.