US 12,457,816 B2
Wide channel semiconductor device
Chia-Yu Wei, Hsinchu (TW); Fu-Cheng Chang, Hsinchu (TW); Hsin-Chi Chen, Hsinchu (TW); Ching-Hung Kao, Hsinchu (TW); Chia-Pin Cheng, Hsinchu (TW); Kuo-Cheng Lee, Hsinchu (TW); Hsun-Ying Huang, Hsinchu (TW); and Yen-Liang Lin, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jul. 31, 2023, as Appl. No. 18/362,507.
Application 16/790,386 is a division of application No. 15/591,689, filed on May 10, 2017, granted, now 10,566,361, issued on Feb. 18, 2020.
Application 18/362,507 is a continuation of application No. 17/830,707, filed on Jun. 2, 2022, granted, now 11,784,198.
Application 17/830,707 is a continuation of application No. 16/790,386, filed on Feb. 13, 2020, granted, now 11,380,721, issued on Jul. 5, 2022.
Claims priority of provisional application 62/434,297, filed on Dec. 14, 2016.
Prior Publication US 2023/0378205 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10F 39/00 (2025.01); H10D 30/60 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 64/27 (2025.01); H10F 39/18 (2025.01)
CPC H10F 39/80373 (2025.01) [H10D 30/60 (2025.01); H10D 30/6212 (2025.01); H10D 62/116 (2025.01); H10D 64/513 (2025.01); H10D 64/518 (2025.01); H10F 39/18 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a plurality of isolation structures, wherein each isolation structure of the plurality of isolation structures is spaced from an adjacent isolation structure of the plurality of isolation structures; and
a gate structure comprising:
a first sidewall;
a second sidewall angled with respect to the first sidewall; and
a first surface extending between the first sidewall and the second sidewall, wherein a dimension of the gate structure in a first direction is less than a dimension of each of the plurality of isolation structures in the first direction.