US 12,457,813 B2
Semiconductor device and imaging device
Takahiro Koyanagi, Osaka (JP)
Assigned to PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD., Osaka (JP)
Filed by Panasonic Intellectual Property Management Co., Ltd., Osaka (JP)
Filed on Apr. 10, 2023, as Appl. No. 18/297,677.
Application 18/297,677 is a continuation of application No. PCT/JP2021/036368, filed on Oct. 1, 2021.
Claims priority of application No. 2020-187527 (JP), filed on Nov. 10, 2020.
Prior Publication US 2023/0261012 A1, Aug. 17, 2023
Int. Cl. H10F 39/00 (2025.01); H01L 21/768 (2006.01); H10D 1/00 (2025.01); H10D 1/68 (2025.01); H10F 39/12 (2025.01)
CPC H10F 39/803 (2025.01) [H01L 21/768 (2013.01); H10D 1/042 (2025.01); H10D 1/043 (2025.01); H10D 1/692 (2025.01); H10D 1/716 (2025.01); H10F 39/12 (2025.01); H10F 39/811 (2025.01)] 16 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first capacitor element that includes a first electrode, a second electrode, and a dielectric layer positioned between the first electrode and the second electrode; and
a second capacitor element that includes a third electrode and an insulating layer positioned between the second electrode and the third electrode, wherein
the first capacitor element includes at least one first trench portion,
the first electrode, the second electrode, and the third electrode are stacked on each other in this order,
at least a part of the first electrode, at least a part of the second electrode, and at least a part of the third electrode overlap each other in a plan view,
the dielectric layer includes a first non-overlapping portion that does not overlap the first electrode in the plan view,
the insulating layer includes a second non-overlapping portion that does not overlap the second electrode in the plan view, and
the first non-overlapping portion is positioned at the same height as the second non-overlapping portion in a thickness direction of the semiconductor device.