US 12,457,810 B2
Imaging device comprising net shape wiring
Yuki Okamoto, Sagamihara (JP); Yoshiyuki Kurokawa, Sagamihara (JP); Hiroki Inoue, Atsugi (JP); and Takuro Ohmaru, Zama (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed by Semiconductor Energy Laboratory Co., Ltd., Atsugi (JP)
Filed on Feb. 12, 2024, as Appl. No. 18/438,633.
Application 18/438,633 is a continuation of application No. 17/517,705, filed on Nov. 3, 2021, granted, now 11,908,876.
Application 17/517,705 is a continuation of application No. 15/311,261, granted, now 11,205,669, issued on Dec. 21, 2021, previously published as PCT/IB2015/053951, filed on May 27, 2015.
Claims priority of application No. 2014-118773 (JP), filed on Jun. 9, 2014.
Prior Publication US 2024/0250097 A1, Jul. 25, 2024
Int. Cl. H10F 39/00 (2025.01); H04N 23/54 (2023.01); H10D 30/67 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01); H10D 84/83 (2025.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10F 10/17 (2025.01); H10F 39/12 (2025.01); H10F 39/18 (2025.01); H01L 23/528 (2006.01)
CPC H10F 39/802 (2025.01) [H04N 23/54 (2023.01); H10D 30/6755 (2025.01); H10D 84/0126 (2025.01); H10D 84/038 (2025.01); H10D 84/83 (2025.01); H10D 86/423 (2025.01); H10D 86/481 (2025.01); H10D 86/60 (2025.01); H10F 10/17 (2025.01); H10F 39/016 (2025.01); H10F 39/12 (2025.01); H10F 39/18 (2025.01); H10F 39/803 (2025.01); H10F 39/8033 (2025.01); H10F 39/8037 (2025.01); H10F 39/80377 (2025.01); H10F 39/807 (2025.01); H01L 23/5286 (2013.01)] 8 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a wiring layer having a net shape comprising openings;
a conductive layer configured to be one electrode of a capacitor;
a photoelectric conversion element; and
a first transistor, a second transistor, a third transistor, and a fourth transistor,
wherein light enters the photoelectric conversion element through a lens, a color filter, and one of the openings,
wherein the conductive layer is electrically connected to the wiring layer through a contact plug,
wherein one of a source and a drain of the first transistor is electrically connected to the photoelectric conversion element,
wherein the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,
wherein one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the third transistor,
wherein one of a source and a drain of the fourth transistor is electrically connected to the gate of the second transistor,
wherein a first wiring is electrically connected to the other of the source and the drain of the second transistor,
wherein the first wiring comprises a first region extending in a first direction,
wherein the wiring layer comprises a second region extending along the one of the openings in the first direction,
wherein the first region and the second region overlap with each other along the first direction,
wherein a second wiring is electrically connected to the other of the source and the drain of the third transistor, and
wherein the first wiring and the second wiring are positioned in the same layer.