US 12,457,803 B2
Displaying base plate and manufacturing method thereof, and displaying device
Fuqiang Li, Beijing (CN); Zhen Zhang, Beijing (CN); Zhenyu Zhang, Beijing (CN); Lizhong Wang, Beijing (CN); Ce Ning, Beijing (CN); Yunping Di, Beijing (CN); Zheng Fang, Beijing (CN); Jiahui Han, Beijing (CN); Chenyang Zhang, Beijing (CN); Yawei Wang, Beijing (CN); and Chengfu Xu, Beijing (CN)
Assigned to Beijing BOE Technology Development Co., Ltd., Beijing (CN)
Appl. No. 17/772,761
Filed by BOE Technology Group Co., Ltd., Beijing (CN)
PCT Filed Jun. 29, 2021, PCT No. PCT/CN2021/103216
§ 371(c)(1), (2) Date Apr. 28, 2022,
PCT Pub. No. WO2023/272503, PCT Pub. Date Jan. 5, 2023.
Prior Publication US 2024/0162247 A1, May 16, 2024
Int. Cl. H10D 86/60 (2025.01); H10D 86/01 (2025.01); H10D 86/40 (2025.01)
CPC H10D 86/60 (2025.01) [H10D 86/0231 (2025.01); H10D 86/451 (2025.01); H10D 86/421 (2025.01)] 11 Claims
OG exemplary drawing
 
1. A displaying base plate, comprising a substrate and a first thin film transistor disposed on one side of the substrate, the thin film transistor comprising an active layer, a first insulating layer, and a gate layer which are disposed in stack, wherein
the active layer comprises a source contact area, a drain contact area, and a channel area connecting the source contact area and the drain contact area; the channel area comprises a first channel area, a first resistance area and a second channel area sequentially disposed in a first direction,
the gate layer comprises a first gate and a second gate which are separately disposed; an orthographic projection of the first gate on a plane where the active layer is located covers the first channel area, and an orthographic projection of the second gate on a plane where the active layer is located covers the second channel area,
the displaying base plate comprises an active area and a non-active area located at the periphery of the active area, and the first thin film transistor is located in the active area,
the active area further comprises a data line and scan lines, which are disposed on one side of the substrate that is close to the first thin film transistor; the data line extends in the first direction, the scan lines comprise a first scan line and a second scan line, the first gate extends in a second direction intersecting with the first direction to form the first scan line, the second gate extends in the second direction to form the second scan line, the source contact area is connected to the data line; and an orthographic projection of the channel area on the substrate is located in an orthographic projection range of the data line on the substrate,
the active layer is located on one side of the gate layer that is close to the substrate, a second insulating layer is disposed on one side of the gate layer that is away from the substrate, a drain of the first thin film transistor is disposed on one side of the second insulating layer that is away from the substrate plate, the drain and the drain contact area are connected through via holes formed in the second insulating layer and the first insulating layer, and the drain is also connected to a first transparent electrode layer,
a third insulating layer is disposed on one side of the first transparent electrode layer that is away from the substrate; a second transparent electrode layer is disposed on one side of the third insulating layer that is away from the substrate, the second transparent electrode layer is connected to a first fixed potential input terminal, and an overlap exists between an orthographic projection of the second transparent electrode layer on the substrate and the orthographic projection of the first transparent electrode layer on the substrate,
a fourth insulating layer is disposed on one side of the second transparent electrode layer that is away from the substrate; the data line is disposed on one side of the fourth insulating layer that is away from the substrate plate, and the data line and the source contact area are connected through via holes formed in the fourth insulating layer, the third insulating layer, the second insulating layer and the first insulating layer,
the first transparent electrode layer comprises a first transfer electrode and a second transfer electrode that are integrally formed, the first transfer electrode is connected to the drain, an orthographic projection of the second transfer electrode on the substrate is located in an orthographic projection range of the first scan line, the second scan line, and an area between the first scan line and the second scan line on the substrate,
a first planarization layer is disposed on one side of the data line that is away from the substrate, and a through hole is formed in the first planarization layer, the through hole penetrates through the first planarization layer, the fourth insulating layer and the third insulating layer, to expose the second transfer electrode, and
a third transparent electrode layer, a second planarization layer and a pixel electrode layer are disposed in stack on one side of the first planarization layer that is away from the substrate, wherein the third transparent electrode layer is disposed close to the substrate, an orthographic projection of the third transparent electrode layer on the substrate covers an orthographic projection of the through hole on the substrate, the third transparent electrode layer is configured to connect the pixel electrode layer and the second transfer electrode, and the second planarization layer is configured to planarize the through hole.