US 12,457,798 B2
Dielectric liner for field effect transistors
Zhi-Chang Lin, Zhubei (TW); Shih-Cheng Chen, Taipei (TW); Kuo-Cheng Chiang, Zhubei (TW); Kuan-Ting Pan, Taipei (TW); Jung-Hung Chang, Changhua County (TW); Lo-Heng Chang, Hsinchu (TW); and Chien Ning Yao, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jan. 30, 2024, as Appl. No. 18/427,581.
Application 18/427,581 is a continuation of application No. 17/238,376, filed on Apr. 23, 2021, granted, now 11,929,287.
Prior Publication US 2024/0170337 A1, May 23, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 84/03 (2025.01); H10D 30/67 (2025.01); H10D 84/01 (2025.01)
CPC H10D 84/038 (2025.01) [H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 84/0147 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a stack of semiconductor layers on a substrate;
a spacer structure around end portions of the stack of semiconductor layers; and
a dielectric liner on a sidewall of the end portions of the stack of semiconductor layers, wherein the spacer structure is in contact with the dielectric liner and the end portions of the stack of semiconductor layers.