US 12,457,797 B2
Semiconductor devices and methods of forming the same
Sung-Min Kim, Incheon (KR); Sunhom Steve Paak, Seoul (KR); Heon-Jong Shin, Yongin-si (KR); and Dong-Ho Cha, Seongnam-si (KR)
Assigned to Samsung Electronics Co., Ltd., Suwon-Si (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jun. 2, 2022, as Appl. No. 17/830,396.
Application 17/830,396 is a continuation of application No. 17/523,223, filed on Nov. 10, 2021, granted, now 11,876,019.
Application 17/523,223 is a continuation of application No. 16/833,885, filed on Mar. 30, 2020, granted, now 11,201,086, issued on Dec. 14, 2021.
Application 16/833,885 is a continuation of application No. 15/903,718, filed on Feb. 23, 2018, granted, now 10,643,898, issued on May 5, 2020.
Application 15/903,718 is a continuation of application No. 15/061,200, filed on Mar. 4, 2016, granted, now 9,905,468, issued on Feb. 27, 2018.
Claims priority of application No. 10-2015-0066565 (KR), filed on May 13, 2015.
Prior Publication US 2022/0301939 A1, Sep. 22, 2022
Int. Cl. H10D 30/62 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 84/038 (2025.01) [H10D 84/0151 (2025.01); H10D 84/0158 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a fin;
a first source/drain region and a second source/drain region on the fin;
a first trench that has a first depth and is between the first source/drain region and the second source/drain region;
a lower device isolation layer in the first trench; and
an upper device isolation layer on the lower device isolation layer,
wherein the upper device isolation layer includes an air gap,
wherein the upper device isolation layer is positioned higher than an upper surface of the first source/drain region,
wherein the lower device isolation layer includes a first isolation layer and a second isolation layer on the first isolation layer, and
wherein the first isolation layer comprises a material different than the second isolation layer.