| CPC H10D 84/038 (2025.01) [H10D 30/014 (2025.01); H10D 30/031 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 64/01 (2025.01); H10D 64/017 (2025.01); H10D 64/258 (2025.01); H10D 84/017 (2025.01); H10D 84/0184 (2025.01); H10D 84/0186 (2025.01); H10D 84/85 (2025.01); H10D 30/6757 (2025.01)] | 20 Claims |

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1. A method, comprising:
forming a first transistor comprising a first channel region, a first gate structure surrounding the first channel region, and first source/drain regions on opposite sides of the first gate structure, wherein forming the first transistor comprises:
forming a first one of the first source/drain regions in a first dielectric layer such that a sidewall of the first one of the first source/drain regions is adjacent a sidewall of the first dielectric layer;
forming a second transistor comprising a second channel region, a second gate structure surrounding the second channel region, and second source/drain regions on opposite sides of the second gate structure;
forming a front-side contact on a top end of a first one of the first source/drain regions of the first transistor; and
forming a first back-side contact extending from a bottom end of the first one of the first source/drain regions of the first transistor to a bottom end of a first one of the second source/drain regions of the second transistor, wherein forming the first back-side contact comprises:
forming the first back-side contact in a second dielectric layer, distinct from the first dielectric layer, such that a sidewall of the first back-side contact is adjacent a sidewall of the second dielectric layer and an upper surface of the first back-side contact is adjacent a bottom surface of the first dielectric layer.
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