US 12,457,795 B2
Transistor structure with multiple halo implants having epitaxial layer, high-k dielectric and metal gate
Samar K. Saha, Milpitas, CA (US)
Filed by Samar K. Saha, Milpitas, CA (US)
Filed on Oct. 18, 2022, as Appl. No. 17/968,189.
Application 15/083,172 is a division of application No. 14/229,102, filed on Mar. 28, 2014, granted, now 9,299,702, issued on Mar. 29, 2016.
Application 17/968,189 is a continuation in part of application No. 15/708,973, filed on Sep. 19, 2017, granted, now 11,488,871.
Application 15/708,973 is a continuation in part of application No. 15/083,172, filed on Mar. 28, 2016, granted, now 9,768,074, issued on Sep. 19, 2017.
Claims priority of provisional application 61/881,908, filed on Sep. 24, 2013.
Prior Publication US 2023/0042167 A1, Feb. 9, 2023
Int. Cl. H10D 84/01 (2025.01); H01L 21/02 (2006.01); H01L 21/225 (2006.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/324 (2006.01); H10D 62/17 (2025.01); H10D 84/03 (2025.01); H10D 84/85 (2025.01)
CPC H10D 84/017 (2025.01) [H01L 21/02365 (2013.01); H01L 21/0262 (2013.01); H01L 21/2257 (2013.01); H01L 21/26513 (2013.01); H01L 21/266 (2013.01); H01L 21/324 (2013.01); H10D 62/314 (2025.01); H10D 62/371 (2025.01); H10D 84/013 (2025.01); H10D 84/0135 (2025.01); H10D 84/0147 (2025.01); H10D 84/0151 (2025.01); H10D 84/0167 (2025.01); H10D 84/0188 (2025.01); H10D 84/038 (2025.01); H10D 84/85 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a gate mask on a surface of a substrate, the gate mask having a length that is greater than a target transistor channel length;
ion implanting first conductivity type dopants at a first energy with the gate mask serving as an ion implantation mask to form first halo regions;
forming first spacers on sides of the gate mask;
ion implanting first conductivity type dopants at a second energy with the gate mask and first spacers serving as an ion implantation mask to form second halo regions, the second energy being greater than the first energy;
removing the gate mask and first spacers from the surface;
forming an epitaxial layer over the surface including over the first and second halo regions;
forming a first insulator layer over the surface;
forming a dummy gate mask on the first insulator layer, the dummy gate mask having a length of the target transistor channel length;
ion implanting second conductivity type dopants at a third energy with the dummy gate mask serving as an ion implantation mask to form source-drain extensions, the third energy being less than the second energy;
forming second spacers on sides of the dummy gate mask;
ion implanting second conductivity type dopants at a fourth energy with the dummy gate mask and second spacers serving as an ion implantation mask to form source and drain regions, the fourth energy being greater than the third energy;
forming a surface dielectric layer over the dummy gate mask and second spacers;
planarizing the surface dielectric layer to expose a top surface of the dummy gate mask;
removing the dummy gate mask to create a gate opening between the second spacers;
forming a high-permittivity (hi-K) insulator layer within at least the gate opening, the hi-K insulator layer having a higher permittivity than silicon dioxide;
forming at least first and second metal gate layers within at least the gate opening over the hi-K insulator layer, the first and second metal gate layers comprising at least one metal; and
planarizing to the top of the second spacers to form a metal gate structure for a first type transistor.