| CPC H10D 64/017 (2025.01) [H01L 21/31144 (2013.01); H01L 21/3213 (2013.01); H10D 30/014 (2025.01); H10D 64/01 (2025.01); H10D 64/015 (2025.01); H10D 64/018 (2025.01); H10D 64/021 (2025.01); H10D 84/0167 (2025.01); H10D 84/0186 (2025.01); H10D 84/038 (2025.01); H10D 30/62 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 84/856 (2025.01)] | 17 Claims |
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1. A method for forming a stacked field-effect transistor (FET) device, the method comprising:
forming a bottom FET device comprising a source, a drain, a channel layer between the source and drain, and a bottom gate electrode arranged along the channel layer;
forming a bonding layer of dielectric bonding material over the bottom FET device; and
forming a top FET device on the bonding layer, wherein forming the top FET device comprises:
forming on the bonding layer a fin structure comprising a channel layer;
etching through the bonding layer to form a bonding layer pattern comprising the dielectric bonding material underneath the fin structure;
forming a dummy gate extending across the fin structure;
forming a first spacer layer comprising portions covering side surfaces of the dummy gate to define a dummy gate spacer, and portions covering side surfaces of the fin structure and the bonding layer pattern;
subsequent to forming the first spacer layer, forming cuts in the fin structure and the bonding layer pattern, comprising etching through the fin structure and then the bonding layer pattern at either side of the dummy gate such that a fin structure portion on a bonding layer pattern portion is preserved underneath the dummy gate and the dummy gate spacer, wherein the fin structure portion and the bonding layer pattern portion are located above the bottom gate electrode;
forming recesses underneath the fin structure portion by laterally etching back side surface portions of the bonding layer pattern portion exposed at either side of the dummy gate;
removing the first spacer layer and subsequently forming a second spacer layer covering the side surfaces of the dummy gate and filling the recesses and exposing end surfaces of the channel layer of the fin structure portion at either side of the dummy gate;
wherein, subsequent to forming the second spacer layer, the method further comprises:
epitaxially growing source/drain bodies on the exposed end surfaces of the channel layer;
subsequently, removing the dummy gate selectively to the second spacer layer to form an upper gate cavity portion exposing the fin structure portion;
forming a lower gate cavity portion exposing an upper surface of the bottom gate electrode, comprising removing the bonding layer pattern portion by subjecting the bonding layer pattern portion to an isotropic etching process via the upper gate cavity, wherein the etching process etches the dielectric bonding material selectively to a spacer material of the second spacer layer; and
forming a gate electrode in the upper and lower gate cavity portions, comprising an upper gate electrode portion extending along the channel layer, and a lower gate electrode portion in contact with the upper surface of the bottom gate electrode.
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