US 12,457,784 B2
Semiconductor device with lateral base link region
Jay Paul John, Chandler, AZ (US); and James Albert Kirchgessner, Tempe, AZ (US)
Assigned to NXP B.V., Eindhoven (NL)
Filed by NXP B.V., San Jose, CA (US)
Filed on Dec. 14, 2022, as Appl. No. 18/066,110.
Prior Publication US 2024/0204052 A1, Jun. 20, 2024
Int. Cl. H10D 62/17 (2025.01); H10D 10/01 (2025.01); H10D 10/80 (2025.01); H10D 62/13 (2025.01); H10D 62/10 (2025.01)
CPC H10D 62/177 (2025.01) [H10D 10/021 (2025.01); H10D 10/861 (2025.01); H10D 62/136 (2025.01); H10D 62/115 (2025.01)] 19 Claims
OG exemplary drawing
 
1. A method comprising:
providing a substrate that includes an isolation region that includes dielectric material and a collector region that includes semiconductor material, and a passivation layer disposed on the substrate;
forming an extrinsic base layer on the passivation layer;
forming an intrinsic base layer over the collector region; and
forming a lateral base link region between the extrinsic base layer and the intrinsic base layer, wherein the lateral base link region is disposed on the passivation layer and directly contacts respective side surfaces of the extrinsic base layer and the intrinsic base layer, wherein the lateral base link region is separated from the collector region by at least the passivation layer, and wherein the lateral base link region is formed after forming the intrinsic base layer.