| CPC H10D 62/126 (2025.01) [H01L 21/0334 (2013.01); H10D 30/015 (2025.01); H10D 30/472 (2025.01); H10D 30/475 (2025.01); H10D 30/4755 (2025.01); H10D 62/824 (2025.01); H10D 64/62 (2025.01)] | 4 Claims | 

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               1. A manufacturing method of a gallium nitride (GaN)-based device based on patterned ohmic contact, comprising: 
            step 1, growing a nucleation layer, a buffer layer, a channel layer, an insertion layer, a barrier layer and a cap layer on a substrate layer sequentially in that order; 
                step 2, growing a silicon oxide (SiO2) mask layer on the cap layer; 
                step 3, coating photoresist on the SiO2 mask layer, and photolithographing ohmic contact region patterns on two sides of the photoresist; 
                wherein an axis of each of the ohmic contact region patterns extends along a gate width direction, and opposite edges of the ohmic contact region patterns each comprise a plurality of arc-shaped edges and a plurality of flat edges; and 
                wherein the plurality of arc-shaped edges and the plurality of flat edges are alternately arranged and sequentially connected; and each of the plurality of arc-shaped edges protrudes towards outward; 
                step 4, etching the SiO2 mask layer, the cap layer, the barrier layer, the insertion layer and a part of the channel layer corresponding to the ohmic contact region patterns to form ohmic contact recesses, and removing the photoresist; 
                step 5, epitaxially growing a n-type doped gallium nitride (n+-GaN) material or the n+ a n-type doped indium gallium nitride (n+-InGaN) material on a surface of a product prepared in the step 4; 
                step 6, removing the SiO2 mask layer to form epitaxial layers; 
                step 7, preparing a source electrode and a drain electrode on the epitaxial layers; 
                step 8, preparing a mesa isolation; 
                step 9, depositing a passivation layer on surfaces of the epitaxial layers and the cap layer, removing the passivation layer deposited on the source electrode and the drain electrode, and preparing a gate groove; 
                step 10, preparing a gate electrode; and 
                step 11, performing metal interconnect to obtain the GaN-based device based on patterned ohmic contact; wherein the GaN-based device based on patterned ohmic contact comprises: 
                the substrate layer, the nucleation layer, the buffer layer, the channel layer, the insertion layer, the barrier layer and the cap layer sequentially arranged in that order from bottom to top; 
                  the ohmic contact recesses, defined on two ends of the cap layer respectively and extending into the channel layer; wherein an axis of each of the ohmic contact recesses extends along the gate width direction; 
                  the gate electrode, located between the ohmic contact recesses; 
                  wherein a side wall of each of the ohmic contact recesses close to the gate electrode comprises a plurality of arc-shaped side walls and a plurality of flat side walls; 
                    wherein the plurality of arc-shaped side walls and the plurality of flat side walls are alternately arranged and sequentially connected; and each of the plurality of arc-shaped side walls protrudes towards a direction of the gate electrode; 
                  the epitaxial layers, disposed in the ohmic contact recesses respectively, wherein an upper end of each of the epitaxial layers is located above the cap layer; and 
                  the passivation layer, covered on the cap layer and the epitaxial layers, wherein the source electrode and the drain electrode penetrate through the passivation layer and are disposed on the epitaxial layers respectively; and the gate electrode penetrates through the passivation layer and extends onto the cap layer; and 
                wherein the epitaxial layers are made from the n+-GaN material or the n+-InGaN material. 
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