US 12,457,780 B2
Semiconductor device with void under source/drain region for backside contact
Ruilong Xie, Niskayuna, NY (US); Alexander Reznicek, Troy, NY (US); Daniel Schmidt, Niskayuna, NY (US); and Tsung-Sheng Kang, Ballston Lake, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Dec. 1, 2022, as Appl. No. 18/073,024.
Prior Publication US 2024/0186374 A1, Jun. 6, 2024
Int. Cl. H10D 62/10 (2025.01); H01L 21/74 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01); H10D 64/23 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 62/121 (2025.01) [H01L 23/481 (2013.01); H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6757 (2025.01); H10D 62/151 (2025.01); H10D 64/017 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0149 (2025.01); H10D 84/038 (2025.01)] 6 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a field effect transistor (FET);
a frontside contact that wires a first source/drain (S/D) epitaxial (epi) of the FET to a back end of line (BEOL) interconnect;
a placeholder recess disposed under the first S/D epi;
a sacrificial placeholder that lines the placeholder recess; and
a void between the sacrificial placeholder and the first S/D epi,
wherein the void is configured to provide an open space within which the first S/D epi can grow and increase a surface area of the first S/D epi.