US 12,457,778 B2
Conductive contacts wrapped around epitaxial source or drain regions
Leonard P. Guler, Hillsboro, OR (US); Gilbert Dewey, Beaverton, OR (US); Saurabh Morarka, Portland, OR (US); Sikandar Abbas, Forest Grove, OR (US); and Mohammad Hasan, Aloha, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Feb. 25, 2022, as Appl. No. 17/681,263.
Prior Publication US 2023/0275124 A1, Aug. 31, 2023
Int. Cl. H01L 29/06 (2006.01); H01L 27/088 (2006.01); H01L 29/423 (2006.01); H01L 29/786 (2006.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 84/83 (2025.01)
CPC H10D 62/121 (2025.01) [H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 84/83 (2025.01)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit comprising:
a first semiconductor device having a subfin and one or more first semiconductor bodies extending between a first source or drain region and a second source or drain region;
a second semiconductor device having the subfin and one or more second semiconductor bodies extending between the first source or drain region and a third source or drain region;
a dielectric layer adjacent to the subfin of the first semiconductor device and the second semiconductor device;
a conductive layer that extends completely around the first source or drain region between the one or more first semiconductor bodies and the one or more second semiconductor bodies; and
a conductive contact extending through a thickness of the dielectric layer and contacting the conductive layer from below the first source or drain region.