US 12,457,777 B2
Semiconductor device with deep trench isolation
Kwang Il Kim, Cheongju-si (KR); Min Kuck Cho, Cheongju-si (KR); Jung Hwan Lee, Cheongju-si (KR); Yang Beom Kang, Cheongju-si (KR); and Hyun Chul Kim, Cheongju-si (KR)
Assigned to SK keyfoundry Inc., Cheongju-si (KR)
Filed by SK keyfoundry Inc., Cheongju-si (KR)
Filed on Feb. 22, 2023, as Appl. No. 18/112,753.
Claims priority of application No. 10-2022-0110168 (KR), filed on Aug. 31, 2022.
Prior Publication US 2023/0317777 A1, Oct. 5, 2023
Int. Cl. H01L 29/00 (2006.01); H01L 23/48 (2006.01); H10D 62/10 (2025.01)
CPC H10D 62/115 (2025.01) [H01L 23/481 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first region having a first gate structure disposed on a substrate;
a second region having a second gate structure disposed on the substrate;
a hard mask disposed on the substrate, the first gate structure, and the second gate structure;
a deep trench isolation disposed in the substrate between the first region and the second region, and formed from the hard mask; and
a planarized gap-fill insulating layer disposed on the second gate structure, and disposed inside the deep trench isolation,
wherein a topmost surface of the planarized gap-fill insulating layer and a topmost surface of the hard mask are coplanar.