US 12,457,772 B2
Regeneration anneal of metal oxide thin-film transistors
Dejiu Fan, Santa Clara, CA (US); Yun-chu Tsai, San Jose, CA (US); and Dong Kil Yim, Pleasanton, CA (US)
Assigned to Applied Materials, Inc., Santa Clara, CA (US)
Filed by Applied Materials, Inc., Santa Clara, CA (US)
Filed on May 20, 2022, as Appl. No. 17/664,335.
Prior Publication US 2023/0378368 A1, Nov. 23, 2023
Int. Cl. H10D 30/67 (2025.01); H01L 21/324 (2006.01); H10D 30/01 (2025.01)
CPC H10D 30/6755 (2025.01) [H01L 21/324 (2013.01); H10D 30/031 (2025.01); H10D 30/6757 (2025.01)] 15 Claims
OG exemplary drawing
 
1. A method of forming a thin film transistor (TFT) comprising:
forming a buffer layer over a substrate;
forming a metal oxide channel layer over the buffer layer;
annealing the metal oxide channel layer;
forming a gate insulator layer over the metal oxide channel layer;
forming a gate electrode over the gate insulator layer;
depositing an inter-layer dielectric (ILD) over the gate electrode and the gate insulator layer to form the TFT; then
annealing the TFT for a first annealing condition to form an annealed TFT, wherein the annealed TFT is shorted or comprises a first threshold voltage, the annealed TFT having exposed source and drain electrodes; then
annealing the annealed TFT having exposed source and drain electrodes for a second annealing condition to form a regenerated TFT having a second threshold voltage greater than the first threshold voltage, the second annealing condition comprising a temperature of 150° C. to 275° C.