US 12,457,771 B2
Plug and recess process for dual metal gate on stacked nanoribbon devices
Nicole Thomas, Portland, OR (US); Michael K. Harper, Hillsboro, OR (US); Leonard P. Guler, Hillsboro, OR (US); Marko Radosavljevic, Portland, OR (US); and Thoe Michaelos, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jun. 6, 2024, as Appl. No. 18/736,428.
Application 18/736,428 is a continuation of application No. 16/911,705, filed on Jun. 25, 2020, granted, now 12,046,652.
Prior Publication US 2024/0332389 A1, Oct. 3, 2024
Int. Cl. H10D 30/67 (2025.01); H01L 21/02 (2006.01); H01L 21/768 (2006.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 30/6735 (2025.01) [H01L 21/0228 (2013.01); H01L 21/76897 (2013.01); H10D 62/119 (2025.01); H10D 84/0128 (2025.01); H10D 84/038 (2025.01)] 26 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a plurality of stacked semiconductor channels, comprising:
a first semiconductor channel; and
a second semiconductor channel over the first semiconductor channel, wherein a spacing is between the first semiconductor channel and the second semiconductor channel;
a gate dielectric surrounding the first semiconductor channel and the second semiconductor channel;
a first workfunction metal surrounding the first semiconductor channel, wherein a portion of the first workfunction metal nearest the first semiconductor channel has a first width; and
a second workfunction metal surrounding the second semiconductor channel, wherein a portion of the second workfunction metal nearest the second semiconductor channel has a second width, the second width the same as the first width, the second workfunction metal in contact with the first workfunction metal at an interface between the second workfunction metal and the first workfunction metal.