| CPC H10D 30/6735 (2025.01) [H10D 30/6713 (2025.01); H10D 62/115 (2025.01); H10D 84/013 (2025.01); H10D 84/0151 (2025.01); H10D 84/038 (2025.01)] | 20 Claims |
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1. A semiconductor structure, comprising:
a semiconductor substrate;
a semiconductor active region including a fin base and multiple channels vertically stacked over the fin base, the fin base extruding from the semiconductor substrate and surrounded by a shallow trench isolation (STI) feature;
a dielectric fin disposed on a top surface of the STI feature and distanced from the semiconductor substrate;
a gate stack disposed on the semiconductor substrate and extending to wrap around each of the multiple channels; and
a source/drain feature formed on the fin base and connected to each of the multiple channels, defining an airgap extending to the dielectric fin and being capped by a dielectric layer, wherein the airgap vertically spans from the dielectric layer to the STI feature.
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