US 12,457,769 B2
Method and structure for gate-all-around devices with deep S/D contacts
Chih-Chuan Yang, Hsinchu (TW); Shih-Hao Lin, Hsinchu (TW); and Yu-Kuan Lin, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Aug. 31, 2021, as Appl. No. 17/462,634.
Prior Publication US 2023/0063098 A1, Mar. 2, 2023
Int. Cl. H10D 30/67 (2025.01); H10B 10/00 (2023.01); H10D 30/01 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01)
CPC H10D 30/6735 (2025.01) [H10B 10/125 (2023.02); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6757 (2025.01); H10D 62/121 (2025.01); H10D 64/018 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method comprising:
providing a structure having a substrate, a source/drain (S/D) feature over the substrate, semiconductor channel layers over the substrate and connecting to the S/D feature, a high-k metal gate (HKMG) wrapping around the semiconductor channel layers, a dielectric cap over the HKMG, a contact etch stop layer (CESL) over the S/D feature and on sidewalls of the dielectric cap and the HKMG, and an interlayer dielectric (ILD) layer over the CESL, wherein the semiconductor channel layers are spaced one from another along a direction that is perpendicular to a top surface of the substrate, and wherein the providing comprises:
growing a first portion of the S/D feature vertically over the substrate and laterally over side surfaces of the semiconductor channel layers, wherein the first portion includes Si1-xGex; and
growing a second portion of the S/D feature over the first portion, wherein the second portion is more doped than the first portion, wherein the second portion includes Si1-yGey, and wherein y is greater than x;
etching the ILD layer and the CESL to expose a top portion of the S/D feature;
after the etching of the ILD layer and the CESL, etching the S/D feature, resulting in a S/D contact trench, wherein a bottom surface of the S/D contact trench is below an upper surface of a bottommost layer of the semiconductor channel layers; and
forming a metallic contact in the S/D contact trench.