US 12,457,768 B2
Vertical transistors and methods for forming the same
H. Jim Fulford, Albany, NY (US); Mark I. Gardner, Albany, NY (US); and Partha Mukhopadhyay, Albany, NY (US)
Assigned to Tokyo Electron Limited, Tokyo (JP)
Filed by Tokyo Electron Limited, Tokyo (JP)
Filed on May 20, 2022, as Appl. No. 17/749,938.
Prior Publication US 2023/0378366 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H10D 30/67 (2025.01); H10D 48/36 (2025.01); H10D 84/85 (2025.01); H10D 99/00 (2025.01)
CPC H10D 30/6728 (2025.01) [H10D 48/362 (2025.01); H10D 84/85 (2025.01); H10D 99/00 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a transistor structure comprising:
a metal structure extending along a vertical direction;
a gate dielectric layer having a least a first portion around the metal structure;
a channel layer having at least a first portion around the gate dielectric layer;
a first metal electrode disposed below the metal structure and in electrical contact with a first end of the first portion of the channel layer;
a second metal electrode disposed above the metal structure and in electrical contact with a second end of the first portion of the channel layer;
a third metal electrode disposed above and in electrical contact with the metal structure; and
a dielectric structure disposed between the metal structure and the first metal electrode.