US 12,457,764 B2
Semiconductor device and method for manufacturing semiconductor device
Yusuke Kanda, Toyama (JP)
Assigned to NUVOTON TECHNOLOGY CORPORATION JAPAN, Kyoto (JP)
Filed by Nuvoton Technology Corporation Japan, Kyoto (JP)
Filed on Jan. 7, 2025, as Appl. No. 19/012,337.
Application 19/012,337 is a continuation of application No. PCT/JP2023/027335, filed on Jul. 26, 2023.
Claims priority of provisional application 63/392,691, filed on Jul. 27, 2022.
Prior Publication US 2025/0151310 A1, May 8, 2025
Int. Cl. H10D 30/47 (2025.01); H10D 30/01 (2025.01); H10D 62/832 (2025.01); H10D 62/85 (2025.01)
CPC H10D 30/471 (2025.01) [H10D 30/015 (2025.01); H10D 62/8325 (2025.01); H10D 62/8503 (2025.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a Si substrate;
a back electrode provided below the Si substrate;
a SiC layer provided above the Si substrate;
a semiconductor layer provided above the SiC layer and made of a group III nitride semiconductor;
a source electrode and a drain electrode provided above the semiconductor layer;
a gate electrode in contact with the semiconductor layer;
an intermediate layer provided in an opening that is formed in at least the SiC layer;
a metal layer provided above the opening; and
a conductor provided inside a through via that passes through the intermediate layer and the Si substrate, and electrically connected with the back electrode and the metal layer, wherein
the metal layer covers the through via,
the intermediate layer is provided between the SiC layer and the conductor,
the intermediate layer is a metal nitride layer or a silicon oxide layer,
the opening has a bottom from which the Si substrate is exposed, and
the intermediate layer is separated from the back electrode.