US 12,457,759 B2
Semiconductor arrangement and method of manufacture
Hung-Te Lin, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-chu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED, Hsin-Chu (TW)
Filed on Mar. 14, 2022, as Appl. No. 17/693,604.
Claims priority of provisional application 63/224,904, filed on Jul. 23, 2021.
Prior Publication US 2023/0028453 A1, Jan. 26, 2023
Int. Cl. H10D 12/00 (2025.01); H10D 12/01 (2025.01); H10D 62/13 (2025.01); H10D 64/01 (2025.01)
CPC H10D 12/411 (2025.01) [H10D 12/01 (2025.01); H10D 62/137 (2025.01); H10D 64/01 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor arrangement, comprising:
a collector region comprising a bottom portion and a sidewall portion extending from the bottom portion to a first surface of a semiconductor layer;
a drift region over the collector region;
a buffer layer between the collector region and the drift region and having an uppermost surface co-planar with the first surface of the semiconductor layer;
a body region over the drift region;
a first body contact and a second body contact in the body region;
an emitter contact contacting the first body contact, the second body contact, and the body region;
a collector contact contacting a first surface of the sidewall portion of the collector region coplanar with the first surface of the semiconductor layer, wherein the collector contact is spaced apart from drift region;
a first gate structure directly contacting the drift region, the body region, and the first body contact, wherein in a first direction parallel to the first surface of the semiconductor layer, a length of the emitter contact is less than a length of the first gate structure; and
a second gate structure separated from the first gate structure and directly contacting the drift region, the body region, and the second body contact, wherein the first direction is perpendicular to a direction extending from the first gate structure to the second gate structure.