| CPC H10B 63/30 (2023.02) [H10B 61/22 (2023.02); H10D 30/6755 (2025.01); H10D 62/80 (2025.01); H10D 99/00 (2025.01)] | 20 Claims |
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1. A method for forming a memory device, comprising:
forming a lower interconnect metal line over a substrate;
forming a selector channel over the lower interconnect metal line;
forming a memory cell over the selector channel; and
forming a selector gate dielectric continuously extending to cover entire sidewalls of the selector channel and the memory cell;
forming a selector gate electrode wrapping around the selector gate dielectric with an upper sidewall and an upper lateral surface of the selector gate dielectric extending above the selector gate electrode; and
forming an upper interconnect metal line disposed over the memory cell;
wherein the selector gate electrode is formed extending laterally and shared by multiple additional selector channels.
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