US 12,457,752 B2
High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor
Sasikanth Manipatruni, Portland, OR (US); Rajeev Kumar Dokania, Beaverton, OR (US); and Ramamoorthy Ramesh, Moraga, CA (US)
Assigned to Kepler Computing Inc., San Francisco, CA (US)
Filed by Kepler Computing Inc., San Francisco, CA (US)
Filed on Aug. 18, 2022, as Appl. No. 17/820,865.
Application 17/820,865 is a continuation of application No. 16/287,953, filed on Feb. 27, 2019, granted, now 11,476,260.
Prior Publication US 2022/0392907 A1, Dec. 8, 2022
Int. Cl. H10B 53/30 (2023.01); G11C 11/22 (2006.01); H01L 21/02 (2006.01); H10B 12/00 (2023.01); H10B 53/20 (2023.01); H10D 1/68 (2025.01); H10D 30/62 (2025.01)
CPC H10B 53/30 (2023.02) [G11C 11/221 (2013.01); G11C 11/2255 (2013.01); G11C 11/2257 (2013.01); H01L 21/02197 (2013.01); H10B 12/36 (2023.02); H10B 53/20 (2023.02); H10D 1/682 (2025.01); H10D 1/684 (2025.01); H10D 1/694 (2025.01); H10D 1/696 (2025.01); H10D 1/716 (2025.01); H10D 30/6211 (2025.01)] 13 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a transistor having a source, a drain, and a gate;
a word-line coupled to the gate;
a bit-line coupled to one of the source or drain of the transistor;
a plate-line; and
a capacitive structure coupled to one of the source or drain of the transistor through one or more vias, and to the plate-line, wherein the capacitive structure comprises:
a first ferroelectric material having a first inverted u-shape;
a second ferroelectric material having a second inverted u-shape;
a first conductive oxide inside a first gap area of the first inverted u-shape, wherein the first conductive oxide abuts inner sidewalls of the first ferroelectric material, wherein the first conductive oxide fully fills the first gap area;
a second conductive oxide inside a second gap area of the second inverted u-shape, wherein the second conductive oxide abuts inner sidewalls of the second ferroelectric material, and wherein the second conductive oxide fully fills the second gap area;
a third conductive oxide between a first outer sidewall of the first ferroelectric material and a first outer sidewall of the second ferroelectric material;
an electrode that abuts the first ferroelectric material and the second ferroelectric material such that the electrode abuts bottom surfaces of the first inverted u-shape of the first ferroelectric material and of the second inverted u-shape of the second ferroelectric material, wherein the electrode couples to the source or the drain of the transistor;
a fourth conductive oxide that abuts a second outer sidewall of the first ferroelectric material;
a fifth conductive oxide that abuts a second outer sidewall of the second ferroelectric material; and
a sixth conductive oxide that abuts upper surfaces of the first inverted u-shape of the first ferroelectric material and of the second inverted u-shape of the second ferroelectric material, wherein the sixth conductive oxide abuts portions of the third conductive oxide, the fourth conductive oxide, and the fifth conductive oxide.